A processor generally includes several processing units operating in parallel. As processing units, an arithmetic and logic unit, an addressing unit and a branch-handling unit are conventionally used. In addition to these processing units, the processor generally includes a control unit or central unit which communicates with the program memory and issues individual instructions, which are also widely called micro-instructions, to the various processing units.
Furthermore, the processor may have a decoupled architecture for allowing a higher speed of execution of the instructions after an initial latency time. The principle of a decoupled architecture is already known to those skilled in the art. Reference is directed to European Patent Application Nos. 949,565 and 1,050,799, for example. The principle of a decoupled architecture will now be reiterated briefly, and those skilled in the art can refer to the abovementioned European patent applications for further details, if necessary.
In addition to the abovementioned processing units, a memory interface is provided which contains a memory of the FIFO-type (first in/first out) intended to receive and to store, temporarily, the data contained in a data memory. A FIFO-type memory may be formed, for example, from two banks of an SRAM memory.
In a decoupled architecture, an instruction for loading memory stored data into a register is partitioned into two micro-instructions or instructions. A first instruction is transmitted to the addressing module (addressing unit) which calculates the actual address of the data in the data memory. The other instruction, which is an instruction for loading into the register in question, is temporarily stored in a FIFO memory associated with the arithmetic and logic unit. This second instruction remains on hold until the memory stored data, derived by the addressing unit, is available. When it is, the register concerned is then actually updated.
After an initial latency time, the addressing unit has drawn ahead of the arithmetic and logic unit. The machine is then decoupled. As seen from the arithmetic and logic unit, the imaginary latency is zero. However, since the instructions intended for the arithmetic and logic unit are processed in a time dependent order, as they are stored in a FIFO, it is entirely possible for a first instruction for loading data stored in a first register to be, at a given instant, stored at the head of the FIFO, and consequently ready to be delivered to the pipeline stages of the processing unit. It is also possible for a second instruction involving different registers of the first register to be stored just behind this first loading instruction. As long as this first loading instruction remains blocked at the head of the FIFO awaiting the memory stored data derived by the addressing unit, the second instruction, immediately behind it, also remains blocked since it is completely independent of the blocked instruction at the head of the FIFO.